This invention relates to semiconductor devices, and more particularly, to a low voltage level shifter circuit.
There is a constant motivation to reduce power consumption for integrated circuits due to packaging requirements, as well as for portable applications. One approach is to use low voltage signaling for buses whenever possible.
Low voltage signaling is attractive to designers since it dramatically reduces the power consumption requirements and leads to decreased electromigration in the conductors of the integrated circuit. With reduced electromigration, the chances of developing voids and shorts in the conductors are greatly reduced. Furthermore, lower power consumption also leads to decreased electrical noise, as less charge is dumped on the ground and power buses at any given time.
FIG. 1 depicts a conventional low voltage buffer and latch 100. The circuit comprises an input buffer stage 110 coupled to a latch stage 112. Low voltage input at input port QRWD may swing from 0V to 1V, which is lower than the full internal device voltage, VDD. Output voltage at output port SRWD may range from 0V to 2V. When the enable signal, ENB, is active high, the circuit drives and latches the data at the input read-write data port, RWD. When ENB goes low, the circuit is disabled and the data at QRWD is latched.
To appreciate the problems encountered when low voltage signals are employed in an inverter-based voltage level shifter circuit, consider the situation when a logically low signal is presented at the input QRWD (e.g. around 0 V). In this case, not only will transistors 118 and 121 be turned on as expected, there will be leakage paths through transistors 126 and 128 of inverter 116 and transistors 130 and 132 of inverter 114.
The presence of leakage current significantly degrades the signal at the output and greatly increases power dissipation. As can be appreciated from the above discussion, it is desirable to provide a low voltage latch circuit that eliminates the current leakage problem.
The invention relates, in one embodiment, to a method for implementing a low voltage level shifter circuit with an embedded latch on a signal line having thereon low voltage signals. The low voltage signals have a voltage level that is below the full internal device voltage, Vdd.
The low voltage level shifter circuit is configured to latch the low voltage input signal and output a voltage signal with a voltage range that is higher than the voltage range associated with the low voltage input signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the level shifter circuit. The input stage is configured to receive the low voltage signal on the signal line. The input stage is also coupled to a level shifting stage that is configured to output a set of level shifting stage control signals responsive to the low voltage input signal. The level shifter control signals are coupled to a latching stage, the latching stage being coupled to the input stage. The latching stage is arranged to latch the low voltage input signal received at the input stage. The method further includes coupling the output node to the level shifting stage. The output node is also coupled to the second portion of the signal line to output a higher voltage level signal.
In another embodiment, the invention relates to a method, for implementing a low voltage level shifter circuit with an embedded latch on a signal line having thereon low voltage signals. The method includes receiving the first low voltage signal using an input stage of the level shifter circuit, the input stage being coupled to the input node. In addition, the method includes forming, using a level shifting stage of the low voltage level shifter circuit, a set of control signals responsive to the low voltage input signal. The voltage range associated with the control signals is higher than the voltage range of the low voltage level input signal. Furthermore, there is included latching the low voltage input signal within a latching stage of the low voltage level shifter circuit. The method further includes outputting an output voltage signal from the level shifting stage control signals. The voltage range associated with the output signal is higher than the voltage range of the low voltage input signal.
In another embodiment, the invention relates to a method for implementing a low voltage repeater circuit with an embedded latch, configured to be coupled to a signal line having thereon low voltage signals. The low voltage levels have a voltage level below Vdd. The method includes coupling an input node to the first portion of the signal line to receive a first low voltage input signal. The input node is also coupled to an input stage of the repeater circuit, the input stage being configured to receive the first low voltage signal on the signal line. Furthermore, the input stage is coupled to a level shifting and latching stage that is arranged to latch the first low voltage input signal and output a set of level shifting stage control signals responsive to the first low voltage signal. The level shifting and latching stage boosts the output control signals, causing the voltage range associated with the set of level shifting stage control signals to be higher than the voltage range of the first low voltage signal. The method further includes coupling the level shifting and latching stage to the output stage of the repeater circuit. The output stage is configured to output a low voltage level signal and is coupled to an output node, which is coupled to the second portion of the signal line.
These and additional features of the present invention will be described in more detail in the following figures and detailed description of the invention.